xt-sys/exectos
xt-sys/exectos
3
5
Fork 3
Code Issues 3 Pull Requests 1 Actions Projects 1 Releases Wiki Activity

Added 8259 PIC support #5

Merged
belliash merged 12 commits from :master into master 2023-11-29 20:07:17 +01:00
Conversation 0 Commits 12 Files Changed 4 +50 -111
10 changed files with 50 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit 0efd9ade59 - Show all commits

13
sdk/xtdk/amd64/hltypes.h
View File

@ -64,6 +64,19 @@
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* 8259 PIC commands */
#define PIC_ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
#define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */
#define PIC_ICW1_INTERVAL4 0x04 /* Call address interva l 4 (8) */
#define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
#define PIC_ICW1_INIT 0x10 /* Initialization - required! */
#define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
#define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */
#define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
#define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37

19
sdk/xtdk/hltypes.h
View File

@ -90,25 +90,6 @@
#define COMPORT_REG_MSR 0x06 /* Modem Status Register */
#define COMPORT_REG_SR 0x07 /* Scratch Register */
/* 8259 PIC ports */
#define PIC_MASTER_COMMAND 0xA0
#define PIC_MASTER_DATA 0xA1
#define PIC_SLAVE_COMMAND 0x20
#define PIC_SLAVE_DATA 0x21
/* 8259 PIC commands */
#define PIC_ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
#define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */
#define PIC_ICW1_INTERVAL4 0x04 /* Call address interva l 4 (8) */
#define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
#define PIC_ICW1_INIT 0x10 /* Initialization - required! */
#define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
#define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */
#define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
#define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */
/* APIC Register Address Map */
belliash marked this conversation as resolved Outdated
belliash commented 2023-11-26 15:29:34 +01:00
Outdated
Review
Copy Link

Does any other platform than x86 and x86_64 support 8259 PIC? If not, this should be architecture specific.

Does any other platform than x86 and x86_64 support 8259 PIC? If not, this should be architecture specific.
typedef enum _APIC_REGISTER
{

13
sdk/xtdk/i686/hltypes.h
View File

@ -69,6 +69,19 @@
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* 8259 PIC commands */
#define PIC_ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
#define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */
#define PIC_ICW1_INTERVAL4 0x04 /* Call address interva l 4 (8) */
#define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
#define PIC_ICW1_INIT 0x10 /* Initialization - required! */
#define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
#define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */
#define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
#define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37

16
xtoskrnl/hl/amd64/ioport.c
View File

@ -143,19 +143,3 @@ HlIoPortOutShort(IN USHORT Port,
: "a" (Value),
"Nd" (Port));
}
/**
* Sends a 0x00 byte to an unused IO port.
* This operation takes 1 - 4 microseconds and functions as an
* imprecise wait function.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlIoPortWait(VOID)
{
HlIoPortOutByte(0x80, 0x00);
}

16
xtoskrnl/hl/i686/ioport.c
View File

@ -143,19 +143,3 @@ HlIoPortOutShort(IN USHORT Port,
: "a" (Value),
"Nd" (Port));
}
/**
* Sends a 0x00 byte to an unused IO port.
* This operation takes 1 - 4 microseconds and functions as an
* imprecise wait function.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlIoPortWait(VOID)
{
HlIoPortOutByte(0x80, 0x00);
}

43
xtoskrnl/hl/pic.c
View File

@ -21,25 +21,25 @@ VOID
HlInitializePic(VOID)
{
/* Start in cascade mode */
HlWritePic(PIC_MASTER_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
HlWritePic(PIC_SLAVE_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
HlWritePic(PIC1_CONTROL_PORT, PIC_ICW1_INIT | PIC_ICW1_ICW4);
HlWritePic(PIC2_CONTROL_PORT, PIC_ICW1_INIT | PIC_ICW1_ICW4);
/* Master PIC Vector offset */
HlWritePic(PIC_MASTER_DATA, 0x20);
/* Slave PIC Vector offset */
HlWritePic(PIC_SLAVE_DATA, 0x28);
/* PIC Vector offset */
HlWritePic(PIC1_DATA_PORT, 0x20);
HlWritePic(PIC2_DATA_PORT, 0x28);
belliash marked this conversation as resolved Outdated
belliash commented 2023-11-26 15:37:58 +01:00
Outdated
Review
Copy Link

What do you think about putting an empty line before each comment? In my opinion it is easy to read, if comment says what does below block of code do and each block ends up with an empty line.

What do you think about putting an empty line before each comment? In my opinion it is easy to read, if comment says what does below block of code do and each block ends up with an empty line.
/* Tell Master PIC that there is a Slave PIC */
HlWritePic(PIC_MASTER_DATA, 4);
HlWritePic(PIC1_DATA_PORT, 4);
/* Tell Slave PIC its cascade identity */
HlWritePic(PIC_SLAVE_DATA, 2);
HlWritePic(PIC2_DATA_PORT, 2);
/* Tell Master PIC to use 8086 mode */
HlWritePic(PIC_MASTER_DATA, PIC_ICW4_8086);
/* Tell Slave PIC to use 8086 mode */
HlWritePic(PIC_SLAVE_DATA, PIC_ICW4_8086);
/* Tell PIC to use 8086 mode */
HlWritePic(PIC1_DATA_PORT, PIC_ICW4_8086);
HlWritePic(PIC2_DATA_PORT, PIC_ICW4_8086);
/* Mask all IRQs by default */
/* This makes sure we don't get any interrupts we can't handle yet. */
for (UCHAR Irq = 0; Irq < 16; Irq++)
belliash marked this conversation as resolved Outdated
belliash commented 2023-11-26 15:18:26 +01:00
Outdated
Review
Copy Link

Do we need to mask all IRQs if we finally disable PIC and use APIC? Do we want to support PIC as a failover?

Do we need to mask all IRQs if we finally disable PIC and use APIC? Do we want to support PIC as a failover?
Ghost commented 2023-11-28 17:06:45 +01:00
Outdated
Review
Copy Link

I have not found any mention of IRQs being explicitly masked or unmasked in any documents, so I masked them so the kernel doesn't get interrupted when the IRQ isn't ready to be served yet (in the case that PIC is indeed used as a failsafe).

I have not found any mention of IRQs being explicitly masked or unmasked in any documents, so I masked them so the kernel doesn't get interrupted when the IRQ isn't ready to be served yet (in the case that PIC is indeed used as a failsafe).
{
HlSetMaskIrqPic(Irq);
@ -58,14 +58,14 @@ HlInitializePic(VOID)
*/
XTCDECL
VOID
HlSetMaskIrqPic(UINT Irq)
HlSetMaskIrqPic(UCHAR Irq)
{
UINT Port;
if(Irq < 8) {
Port = PIC_MASTER_DATA;
Port = PIC1_DATA_PORT;
} else {
Port = PIC_SLAVE_DATA;
Port = PIC2_DATA_PORT;
Irq -= 8;
}
@ -84,14 +84,14 @@ HlSetMaskIrqPic(UINT Irq)
*/
XTCDECL
VOID
HlClearMaskIrqPic(UINT Irq)
HlClearMaskIrqPic(UCHAR Irq)
{
UINT Port;
if(Irq < 8) {
Port = PIC_MASTER_DATA;
Port = PIC1_DATA_PORT;
} else {
Port = PIC_SLAVE_DATA;
Port = PIC2_DATA_PORT;
Irq -= 8;
}
@ -109,8 +109,8 @@ XTCDECL
VOID
HlDisablePic(VOID)
{
HlIoPortOutByte(PIC_MASTER_DATA, 0xFF);
HlIoPortOutByte(PIC_SLAVE_DATA, 0xFF);
HlIoPortOutByte(PIC1_DATA_PORT, 0xFF);
HlIoPortOutByte(PIC2_DATA_PORT, 0xFF);
}
XTFASTCALL
@ -119,8 +119,9 @@ HlWritePic(IN UCHAR Register, IN UCHAR Value)
{
/* Send data */
HlIoPortOutByte(Register, Value);
/* Wait for some time to make sure PIC has processed the data */
HlIoPortWait();
HlIoPortOutByte(0x80, 0x00);
}
/**

18
xtoskrnl/includes/amd64/hl.h
View File

@ -1,18 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/amd64/hl.h
* DESCRIPTION: AMD64 hardware abstraction layer routines
* DEVELOPERS: Jozef Nagy <schkwve@gmail.com>
*/
#ifndef __XTOSKRNL_AMD64_HL_H
#define __XTOSKRNL_AMD64_HL_H
#include <xtos.h>
XTCDECL
VOID
HlIoPortWait(VOID);
#endif /* __XTOSKRNL_AMD64_HL_H */

4
xtoskrnl/includes/hl.h
View File

@ -19,11 +19,11 @@ HlInitializePic(VOID);
XTCDECL
VOID
HlSetMaskIrqPic(UINT Irq);
HlSetMaskIrqPic(UCHAR Irq);
XTCDECL
VOID
HlClearMaskIrqPic(UINT Irq);
HlClearMaskIrqPic(UCHAR Irq);
XTCDECL
VOID

18
xtoskrnl/includes/i686/hl.h
View File

@ -1,18 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/i686/hl.h
* DESCRIPTION: I686 hardware abstraction layer routines
* DEVELOPERS: Jozef Nagy <schkwve@gmail.com>
*/
#ifndef __XTOSKRNL_I686_HL_H
#define __XTOSKRNL_I686_HL_H
#include <xtos.h>
XTCDECL
VOID
HlIoPortWait(VOID);
#endif /* __XTOSKRNL_I686_HL_H */

1
xtoskrnl/includes/xtos.h
View File

@ -22,7 +22,6 @@
#include ARCH_HEADER(globals.h)
#include ARCH_HEADER(ar.h)
#include ARCH_HEADER(hl.h)
#include ARCH_HEADER(ke.h)
#include ARCH_HEADER(mm.h)
#include ARCH_HEADER(rtl.h)